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CYK128K16SCCB
2-Mbit (128K x 16) Pseudo Static RAM
Features
* Advanced low-power MoBL(R) architecture * High speed: 55 ns, 70 ns * Wide voltage range: 2.7V to 3.3V * Typical active current: 1 mA @ f = 1 MHz * Low standby power * Automatic power-down when deselected
Functional Description[1]
The CYK128K16SCCB is a high-performance CMOS pseudo static RAM (PSRAM) organized as 128K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL) in portable applications such as cellular telephones. The device can be put into standby mode, reducing power consumption dramatically when deselected (CE1 LOW, CE2 HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the chip is deselected (CE1 HIGH, CE2 LOW) or OE is deasserted HIGH), or during a write operation (Chip Enabled and Write Enable WE LOW). Reading from the device is accomplished by asserting the Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table for a complete description of read and write modes.
Logic Block Diagram
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DATA IN DRIVERS
ROW DECODER
128K x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER BHE WE OE BLE BHE BLE CE2 CE1
CE2 CE1
A11
A12
A13
A14
A15
Pow er Down Circuit
Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05525 Rev. *F
*
3901 North First Street
A16
*
San Jose, CA 95134 * 408-943-2600 Revised January 26, 2005
CYK128K16SCCB
Pin Configuration[2, 3, 4]
48Ball VFBGA
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC
2 OE BHE I/O10 I/O11
Top View 4 3
5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11
6 CE2 I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H
A0 A3 A5 NC
A1 A4 A6 A7 A16 A15 A13 A10
I/O12 DNU I/O13 NC A8 A14 A12 A9
Product Portfolio
Power Dissipation VCC Range (V) Product CYK128K16SCCB Min. 2.7 Typ. 3.0 Max. 3.3 Operating, ICC (mA) Speed (ns) 55 70 f = 1 MHz Typ.[5] 1 Max. 5 f = fMAX Typ.[5] 14 8 Max. 22 15 Standby, ISB2 (A) Typ.[5] 9 Max. 40
Note: 2. Ball D3, H1, G2, H6 are the address expansion pins for the 4-Mb, 8-Mb, 16-Mb, and 32-Mb densities respectively. 3. NC "no connect"--not connected internally to the die. 4. DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper application. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25C.
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CYK128K16SCCB
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage to Ground Potential ................ -0.4V to 4.6V DC Voltage Applied to Outputs in High-Z State[6, 7, 8] ....................................... -0.4V to 3.3V DC Input Voltage[6, 7, 8] ................................... -0.4V to 3.3V Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA
Operating Range
Range Ambient Temperature (TA) VCC
Industrial
-25C to +85C
2.7V to 3.3V
DC Electrical Characteristics (Over the Operating Range)
CYK128K16SCCB-55 Parameter. VCC VOH VOL VIH VIL IIX IOZ ICC Description Supply Voltage Output HIGH Voltage IOH = -0.1 mA Output LOW Voltage IOL = 0.1 mA Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current f=0 GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC VCC = 3.3V, IOUT = 0mA, f = 1 MHz CMOS level Test Conditions Min. 2.7 VCC - 0.4 0.4 0.8 * VCC -0.4 -1 -1 14 1 40 VCC + 0.4 0.4 +1 +1 22 5 250 0.8 * VCC -0.4 -1 -1 8 1 40 Typ.[5] 3.0 Max. 3.3 CYK128K16SCCB-70 Min. 2.7 VCC - 0.4 0.4 VCC + 0.4 0.4 +1 +1 15 5 250 A Typ.[5] Max. 3.3 Unit V V V V V A A mA
ISB1
Automatic CE CE1 > VCC - 0.2V, CE2 < 0.2V Power-down Current VIN > VCC - 0.2V, VIN < 0.2V, --CMOS Inputs f = fMAX(Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = 3.3V Automatic CE CE1 > VCC - 0.2V, CE2 < 0.2V Power-down Current VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC =3.3V --CMOS Inputs
ISB2
9
40
9
40
A
Capacitance[9]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz VCC = VCC(typ) Max. 8 8 Unit pF pF
Thermal Resistance[9]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. VFBGA 55 17 Unit C/W C/W
Notes: 6. VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 7. VIL(MIN) = -0.5V for pulse durations less than 20 ns. 8. Overshoot and undershoot specifications are characterized and are not 100% tested. 9. Tested initially and after design or process changes that may affect these parameters.
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CYK128K16SCCB
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC GND 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH 3.0V VCC 22000 22000 11000 1.50 Unit V
Parameters R1 R2 RTH VTH
Switching Characteristics (Over the Operating Range) [10]
CYK128K16SCCB-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE tSK[14] Write Cycle[13] tWC tSCE tAW tHA tSA Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start 55 45 45 0 0 70 55 55 0 0 ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[11, 12] Z[11, 12] Z[11, 12] 5 25 55 5 10 0 5 25 10 5 25 5 25 70 OE HIGH to High 5 55 25 5 25 55[14] 55 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. CYK128K16SCCB-70 Min. Max. Unit
CE1 LOW and CE2 HIGH to Low BLE/BHE LOW to Data Valid BLE/BHE LOW to Low BLE/BHE HIGH to Address Skew Z[11, 12] High-Z[11, 12]
CE1 HIGH and CE2 LOW to High Z[11, 12]
Notes: 10. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance 11. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. High-Z and Low-Z parameters are characterized and are not 100% tested. 13. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 14. To achieve 55-ns performance, the read access should be Chip-enable controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.
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CYK128K16SCCB
Switching Characteristics (Over the Operating Range) (continued)[10]
CYK128K16SCCB-55 Parameter tPWE tBW tSD tHD tHZWE tLZWE Description WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High Z
[11, 12]
CYK128K16SCCB-70 Min. 55 55 25 0 Max. Unit ns ns ns ns 25 5 ns ns
Min. 40 50 25 0
Max.
25 5
WE HIGH to Low Z[11, 12]
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[14, 15, 16] tRC ADDRESS tSK DATA OUT tOHA tAA DATA VALID
PREVIOUS DATA VALID
Read Cycle 2 (OE Controlled)[14, 16]
ADDRESS
tSK
tRC
CE1
CE2 tACE
BHE/BLE
tHZCE
tLZBE
OE
tDBE
tHZBE
DATA OUT
tLZOE HIGH IMPEDANCE tLZCE t
tDOE DATA VALID
tHZOE HIGH IMPEDANCE ICC
VCC PU Notes: 15. Device is continuously selected. OE, CE1 = VIL and CE2 = VIH. 16. WE is HIGH for Read Cycle.
50%
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CYK128K16SCCB
Switching Waveforms (continued)
Write Cycle No. 1(WE Controlled)[13, 14, 17, 18, 19]
tW C ADES D RS tS E C
C1 E
C 22 E CE tA W tS A
W E
tH A tP E W
BE L H /B E
tB W
O E
tS D DT A AI/O
D 'T C R ON AE
tHD
tH D
VL DT A ID A A tH E ZO
Write Cycle 2 (CE1 or CE2 Controlled)[13, 14, 17, 18, 19] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA
WE tBW
BHE/BLE
OE tSD DATA I/O
DON'T CARE
tHD
VALID DATA tHZOE
Notes: 17. Data I/O is high impedance if OE > VIH. 18. If Chip Enable goes INACTIVE simultaneously with WE = HIGH, the output remains in a high-impedance state. 19. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
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CYK128K16SCCB
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)[18, 19] tWC ADDRESS tSCE
CE1
CE2
BHE/BLE
tBW tAW tSA tPWE
t HD
tHA
WE
tSD DATA I/O
DON'T CARE
VALID DATA tHZWE tLZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18, 19]
tC W ADES D RS C1 E
CE2 C2 E
tC SE tW A tW B
tA H
BE L H /B E tA S W E tW PE tD S D T I/ AA O
DN CR O' AE T
t HD
tH D
V LDD T AI AA
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CYK128K16SCCB
Truth Table[20]
CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H L L H L L H Inputs/Outputs High Z High Z High Z Data Out (I/O0-I/O15) Data Out (I/O0-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High Z High Z High Z Data In (I/O0-I/O15) Data In (I/O0-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O15); I/O0 -I/O7 in High Z Mode Deselect/Power-down Deselect/Power-down Deselect/Power-down Read Read Read Output Disabled Output Disabled Output Disabled Write (Upper Byte and Lower Byte) Write (Lower Byte Only) Write (Upper Byte Only) Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 55 70 55 70 Ordering Code CYK128K16SCCBU-55BVI CYK128K16SCCBU-70BVI CYK128K16SCBU-55BVXI CYK128K16SCBU-70BVXI Package Name BV48A BV48A BV48A BV48A Package Type 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Operating Range Industrial Industrial Industrial Industrial
Note: 20. H = Logic HIGH, L = Logic LOW, X = Don't Care.
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CYK128K16SCCB
Package Diagrams
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
MoBL is a registered trademark, and MoBL3 and More Battery Life are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CYK128K16SCCB
Document History Page
Document Title: CYK128K16SCCB 2-Mbit (128K x 16) Pseudo Static RAM Document Number: 38- 05525 REV. ** *A *B ECN NO. Issue Date 215621 218183 225600 See ECN See ECN See ECN Orig. of Change REF REF AJU New data sheet Changed ball E3 on package pinout from DNU to NC Change from Advance Information to Preliminary Changed Ordering code from CYK128K16SCCB to CYK128K16SCCBU Fixed package name typo in `Thermal Resistance' table Changed ball E3 on package pinout from NC to DNU Changed from Preliminary to Final Changed Ambient Temperature with Power Applied from -40C to +85C to -55C to +125C Added Pb-Free parts to the Ordering information Description of Change
*C *D *E *F
234474 263150 263811 313999
See ECN See ECN See ECN See ECN
SYT PCI PCI RKF
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